PCI Configuration Space
7
Target Configuration Space
The PCI specification requires a 256-byte configuration space (header) to define various attributes of the PCI Target, as
shown in Table 7-1 . All registers shown in bold are implemented. Reads of all other registers will return
zero. CorePCIF uses the capability pointer to extend the configuration space. One or two capability structures are
Table 7-1 · PCI Configuration Space
31–24
23–16
15–8
7–0
Address
Base PCI Configuration Space
Device ID
Status
Class Code
Vendor ID
Command
Revision ID
00h
04h
08h
BIST
Header Type
Latency Timer
Cache Line Size
0Ch
Base address #0
Base address #1
Base address #2
Base address #3
Base address #4
Base address #5
CardBus CIS Pointer (optional)
10h
14h
18h
1Ch
20h
24h
28h
Subsystem ID
Subsystem Vendor ID
2Ch
Expansion ROM base address
30h
Reserved
Reserved
Capability Pointer
34h
38h
Max. Latency
Min. Grant
Interrupt Pin
Interrupt Line
3Ch
added. Vendor capability (ID = 9) is added along with optional hot-swap capability (ID = 6).
v4.0
105
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